Technology Scaling Impact on Embedded ADC Design for Telecom Receivers

This paper is concerned with the impact of technology scaling on the choice of A/D converters in telecom receivers. It is shown that the trend of diminishing feature size, together with better matching of passive components, allows the use of A/D topologies traditionally confined to low-frequency, medium-resolution applications. The design of a 10 bit 20 MS/s ADC using the successive approximation algorithm is presented in order to validate the presented concepts. By using a deep-submicron technology, the speed of the chosen architecture is pushed to meet the desired output rate

A 0.8V, 7μA, rail-to-rail input/output, constant Gm operational amplifier in standard digital 0.18μm CMOS

A two-stage amplifier, operational at 0.8V and drawing 7/spl mu/A, has been integrated in a standard digital 0.18/spl mu/m CMOS process. Rail-to-rail operations at the input are enabled by complementary transistor pairs with g/sub m/ control. The efficient rail-to-rail output stage is biased in class AB. The measured DC gain of the amplifier is 75dB, and the unity-gain frequency is 870kHz with a 12pF, 100k/spl Omega/load. Both input and output stage transistors are biased in weak inversion